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W83601R/G/W83602R/G
W83601R/W83601G/ W83602R/W83602G Winbond GPI/O IC
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Publication Release Date: May 26, 2005 Revision 1.0
W83601R/G/W83602R/G
Table of Contents1. 2. 3. 5. 7. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PACKAGE ................................................................................................................................... 3 PIN CONFIGURATION FOR W83601R/602R............................................................................ 4 6.1 7.1 7.2 8. 8.1 W83602R/G Universal General Purpose I/O Port for I2C BUS & ACPI Power Control . 6 Brief of register contents................................................................................................. 7 W83601R/G/W83602R/G Registers Descriptions .......................................................... 8 ACCESS INTERFACE.................................................................................................. 12
8.1.1 8.1.2 Write a data into W83601R/G/W83602R/G register .......................................................12 Read a data from W83601R/G/W83602R/G register......................................................12
REGISTERS ............................................................................................................................... 7
FUNCTION DESCRIPTIONS.................................................................................................... 12
8.2 8.3 8.4
CTLSTRV Timing Waveforms (Only for W83602R/G) ................................................. 13 CTL3VSB Timing Waveforms (Only for W83602R/G).................................................. 13 GPI/O Output Mode : .................................................................................................... 14
8.4.1 8.4.2 8.4.3 GPO output ....................................................................................................................14 INT output.......................................................................................................................14 GPI interrupt status.........................................................................................................14
9.
DC AND AC SPECIFICATION.................................................................................................. 15 9.1 9.2 9.3 Absolute Maximum Ratings .......................................................................................... 15 DC Characteristics ........................................................................................................ 15 AC Characteristics ........................................................................................................ 16
9.3.1 Serial Bus Timing Diagram.............................................................................................16
10. 11.
PACKAGE DRAWING AND DIMENSIONS.............................................................................. 17 REVISION HISTORY ................................................................................................................ 21
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W83601R/G/W83602R/G
1. GENERAL DESCRIPTION
W83601R/G/W83602R/G are general purpose input/output ICs with SMBusTM( I2C ). W83601R/G provides 15 GPI/O pins. W83602R/G provides 10 GPI/O pins and ACPI power control function for STR. W83601R/G/W83602R/G both provides SMBusTM (I2C) address setting pins to set the address during power- on reset or from external reset. W83601R/G SMBusTM Address is:
0
0
1
1
A2 A1 A0 R/W
W83602R/G SMBusTM Address is:
0
0
1
1
0
A1 A0 R/W
W83601R/G/W83602R/G also provides a interrupt to inform system that a transition occurs on General Purpose (GP) input pins.
2. FEATURES
SMBus compliance with 3.3V voltage levels Two ports GPI/O which provides more flexibility Issue interrupts to notify system that an event occurs GP output can be level or pulse mode Interrupt output can be level or pulse mode Internal power-on reset or external RST# pin reset Programmable POWER LED output ACPI power management for Suspend to Ram (STR) (only for W83602R/G)
3. PACKAGE
20-pin SSOP
4. 4. KEY SPECIFICATIONS
Supply Voltage 5V 1 mA typ. 0 - 70 C Operating Supply Current Operating Temperature
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Publication Release Date: May 26, 2005 Revision 1.0
W83601R/G/W83602R/G
5. PIN CONFIGURATION FOR W83601R/602R
W83601R
SCLK SDAT GP20/A0 GP21/A1 GP22/A2 GP10 GP11 GP23 GP24 VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20SSOP VDD RST# GP17/INT GP16 GP15 GP14 GP13 GP12 GP26/INT GP25 SCLK SDAT GP20/A0 GP21/A1 CTL3VSB GP10 GP11 CTLSTRV S5IN# VSS
W83602R
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20SSOP VDD RST# GP17/INT GP16 GP15 GP14 GP13 GP12 PWCTLIN# PS_ON#
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W83601R/G/W83602R/G
6. PIN DESCRIPTION
I/OD24t I/OD12ts I/O21 INt INcd INts OD24 - TTL level bi-directional pin open drain output with 24 mA sink capability - TTL level bi-directional pin open drain output with 12 mA sink capability and schmitt-trigger level input - CMOS level bi-directional pin with 21 mA source-sink capability - TTL level input pin - CMOS level input pin with internal pull down resistor - TTL level Schmitt-trigger input pin - Open drain output pin with 24 mA sink capability
W83601R/G
PIN
Universal General Purpose I/O Port for I2C BUS
I/O FUNCTION
2
SYMBOL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SCL SDA GP20 A0 GP21 A1 GP22 A2 GP10 GP11 GP23 GP24 VSS GP25 GP26 INT GP12 GP13 GP14 GP15 GP16 GP17 INT RST# VDD
INts I/OD12ts I/O21 INcd I/O21 INcd I/O21 INcd I/OD24t I/OD24t I/OD24t I/OD24t PWR I/OD24t I/OD24t OD24 I/OD24t I/OD24t I/OD24t I/OD24t I/OD24t I/OD24t OD24 Ints PWR
SMBus Clock. (I C clock) SMBus bi-directional Data.(I2C data) General Purpose I/O. This pin is a setting pin for SMBus (I2C) address bit 0 during power-on reset or RST# pin reset. General Purpose I/O. This pin is a setting pin for SMBus (I2C) address bit 1 during power-on reset or RST# pin reset. General Purpose I/O. This pin is a setting pin for SMBus (I2C) address bit 2 during power-on reset or RST# pin reset. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. Ground Pin. General Purpose I/O default input. General Purpose I/O default input. Auto-generate Interrupt signal when detecting a transition on GPI inputs. This interrupt is either on pin12 or pin18. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. Auto-generate Interrupt signal when detecting a transition on GPI inputs. This interrupt is either on pin12 or pin18 Reset signal input. Power Pin.
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Publication Release Date: May 26, 2005 Revision 1.0
W83601R/G/W83602R/G
6.1
PIN
W83602R/G Universal General Purpose I/O Port for I2C BUS & ACPI Power Control
SYMBOL I/O FUNCTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
SCL SDA GP20 A0 GP21 A1 CTL3VSB GP10 GP11 CTLSTR S5IN# VSS PS_ON# PWCTLIN# GP12 GP13 GP14 GP15 GP16 GP17 INT
INts I/OD12ts I/O21 INcd I/O21 INcd OD24 I/OD24t I/OD24t OD24 INt PWR OD24 INt I/OD24t I/OD24t I/OD24t I/OD24t I/OD24t I/OD24t OD24 INts PWR
SMBus Clock. (I C clock) SMBus bi-directional Data.(I2C data) General Purpose I/O. This pin is a setting pin for SMBus (I2C) address bit 0 during power-on reset or RST# pin reset. General Purpose I/O. This pin is a setting pin for SMBus (I2C) address bit 1 during power-on reset or RST# pin reset. Control 3VSB and 3VCC power source for ACPI features. General Purpose I/O default input. General Purpose I/O default input. Suspend to RAM power control output. S5# signal input. Ground Pin. ATX power on_off control. Connected to W83627F/HF power control output. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. Auto-generate Interrupt signal when detecting a transition on GPI inputs. Reset signal input. Power Pin.
2
19 20
RST# VDD
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W83601R/G/W83602R/G
7. REGISTERS
7.1 Brief of register contents
R/W DEFAULT REGISTERS DESCRIPTION INDEX
00h 01h 02h 03h 04h 05h 06-07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0E-0F h 10h 11h 12h 13h 14h 15h 16-1F h 20h 21h
R R/W R/W R/W R/W R R R/W R/W R/W R/W R R R R/W R/W R/W R/W R R
00 f0 ff 00 00 70 7f 00 00 00 00 00 00 00 60 12 22
GP Port 1: Input Port Data Register GP Port 1: Output Port Data Register GP Port 1: Polarity Inversion Register GP Port 1: Input/Output Configuration Register GP Port 1: Output style control Register. GP Port 1: Input Latched Data Register. Reserved Register GP Port 2: Input Port Register GP Port 2: Output Port Register GP Port 2: Polarity Inversion Register GP Port 2: Input/Output Configuration Register GP Port 2: Output style control Register. GP Port 2: Input Latched Data Register. Reserved Register GP Port 1: Interrupt Status Register. GP Port 2: Interrupt Status Register GP Port 1: Interrupt Enable Register GP Port 2: Interrupt Enable Register Mode Configuration Register Power LED Configuration Register Reserved Register Chip ID High Byte Register Chip ID Low Byte Register (W83601R/G) Chip ID Low Byte Register (W83602R/G)
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Publication Release Date: May 26, 2005 Revision 1.0
W83601R/G/W83602R/G
7.2 W83601R/G/W83602R/G Registers Descriptions
CR00 (GP Port 1: Input port Data Register, Default 0x--, Read Only) This register is a data port for input only. It reflects the incoming logic levels of the pins whether the pin is defined as an input mode by CR03. It will be inverted data by CR02. Bit 7 ~ 0: GP17 ~ GP10 Input Data Port. CR01 (GP Port 1: Output port Data Register, Default 0x00, Read/Write) This register is a data port for output only. It reflects the outgoing logic levels of the pins whether the pin is defined as an output mode by CR03. This register will reflect the value of output Flip-flop while read access. The output data will be inverted or changed output style by CR02 or CR04. Bit 7 ~ 0: GP17 ~ GP10 Output Data Port. CR02 (GP Port 1: Polarity Inversion Register, Default 0xf0, Read / Write) This register enables polarity inversion of pins defined as input or output by CR03. When set to a "1", the incoming/outgoing port value is inverted. When set to a "0", the incoming/outgoing port value is the same as in data register. Bit 7 ~ 0: GP17 ~ GP10 Polarity Iversion Register. CR03 (GP Port 1: Input/Output Configuration Register, Default 0xff, Read / Write) This register selects Input or Output mode of pins. When set to a "1", respective GPIO port is programmed as an input port. When set to a "0", respective GPIO port is programmed as an output port. Bit 7 ~ 0: GP17 ~ GP10 Input/Output Configuration Register. CR04 (GP Port 1: Output Style Control Register, Default 0x00, Read / Write) This register selects Output style of pins as level or pulse. When set to a "1", respective GPIO port is programmed as a pulse signal. When set to a "0", respective GPIO port is programmed as a level signal. Bit 7 ~ 0: GP17 ~ GP10 Output Style Control Register. CR05 (GP Port 1: Input latched data Register, Default 0x--, Read Only) This register will latch Port 1 data while power on or RST# pin low, which is controlled by CR14h bit 0. Bit 7 ~ 0: GP17 ~ GP10 Input latched data. CR06-07 Reserved Register
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W83601R/G/W83602R/G
CR08 (GP Port 2: Input port Data Register, Default 0x--, Read Only) This register is a data port for input only. It reflects the incoming logic levels of the pins whether the pin is defined as an input mode by CR0B. It will be inverted data by CR0A. Bit 7: Reserved. Bit 6 ~ 0: GP26 ~ GP20 Input Data Port. CR09 (GP Port 2: Output port Data Register, Default 0x00, Read / Write) This register is a data port for output only. It reflects the outgoing logic levels of the pins whether the pin is defined as an output mode by CR0B. This register will reflect the value of output Flip-flop while read access. The output data will be inverted or changed output style by CR0A or CR0C. Bit 7: Reserved. Bit 7 ~ 0: GP26 ~ GP20 Output Data Port. CR0A (GP Port 2: Polarity Inversion Register, Default 0x70, Read / Write) This register enables polarity inversion of pins defined as input or output by CR0B. When set to a "1", the incoming/outgoing port value is inverted. When set to a "0", the incoming/outgoing port value is the same as in data register. Bit 7: Reserved. Bit 6 ~ 0: GP26 ~ GP20 Polarity Inversion Register. CR0B (GP Port 2: Input/Output Configuration Register, Default 0x7f, Read / Write) This register selects Input or Output mode of pins. When set to a "1", respective GPIO port is programmed as an input port. When set to a "0", respective GPIO port is programmed as an output port. Bit 7: Reserved. Bit 6 ~ 0: GP26 ~ GP20 Input/Output Configuration Register. CR0C (GP Port 2: Output Style Control Register, Default 0x00, Read / Write) This register selects Output style of pins as level or pulse. When set to a "1", respective GPIO port is programmed as a pulse signal. When set to a "0", respective GPIO port is programmed as a level signal. Bit 7: Reserved. Bit 6 ~ 0: GP26 ~ GP20 Output Style Control Register. CR0D (GP Port 2: Input latched data Register, Default 0x--, Read Only) This register will latch Port 2 data while power on or RST# pin low, which is controlled by CR14h bit 1. Bit 7: Reserved. Bit 6 ~ 0: GP26 ~ GP20 Input latched data, which bit 2-0 are SMBus address bit A2-A0. CR0E-0F Reserved Register Publication Release Date: May 26, 2005 Revision 1.0
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W83601R/G/W83602R/G
CR10 (GP Port1: Interrupt Status Register, Default 0x00, Read Only) Bit 7-0: = 1, a transition occurs at pin GP17-GP10. If GP17/INT is selected as interrupt function, bit 7 of this register will always be 0. A read to this register will clear this register. CR11 (GP Port2: Interrupt Status Register, Default 0x00, Read Only) Bit 7: = Reserved. Bit 6-0: = 1, a transition occurs at pin GP26-GP20. If GP26/INT is selected as interrupt function, bit 6 of this register will always be 0. A read to this register will clear this register. CR12 (GP Port 1: Interrupt Enable Register, Default 0x00, Read / Write) Bit 7-0: = 0, disable GP17-GP10 interrupt output when interrupt function is selected. CR13 (GP Port 2: Interrupt Enable Register, Default 0x00, Read / Write) Bit 7-5: = Reserved. Bit 6-0: = 0, disable GP26-GP20 interrupt output when interrupt function is selected. CR14 Mode Configuration Register (Default 0x00, Read / Write) Bit 7: = 1, Set GP/INT pin as INT function. 0, Set GP/INT pin as GP function. Bit 6: = 1, Set INT function at GP26 (pin 12). 0, Set INT function at GP17 (pin 18). W83602R/G INT function is only at GP17. Bit 5: = 1, Set INT output pin as pulse mode. 0, set INT output pin as level mode. Bit 4: = 1, Set INT output pin polarity is 1 (normal high) . 0, set INT output pin polarity is 0 (normal low). This bit is only for W83601R. Bit 3: = 1, Port 2 (CR09h-CR0Ch, CR11h, CR13h) registers can be reset to default data by RST# pin. 0 Port 2 (CR09h-CR0Ch) can not be reset by RST# pin. Bit 2: = 1, Port 1 (CR01h-CR04h, CR10h, CR12h) registers can be reset to default data by RST# pin. 0, Port 1 (CR01h-CR04h) can not be reset by RST# pin. Bit 1: = 1, Port 2 CR0Dh can be latched not only by RST# pin but also power-on period. 0, Port 2 CR0Dh can only be latched by power-on period. Bit 0: = 1, Port 1 CR05h can be latched not only by RST# pin but also power-on period. 0, Port 1 CR05h can only be latched by power-on period.
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W83601R/G/W83602R/G
CR15 Power LED Configuration Register (Default 0x00, Read/Write) Priority of LED function is highest. Bit 7: = 1, Enable LED function. 0, Disable LED funciton. When LED function is enabled, GP function is ignored despite of input or output. Bit 6-4: LED frequency selection. = 111, LED pin is tri-state (OD pin) or drived high (O pin). = 110, LED pin is a 1 Hz toggle pulse with 50 duty cycle. = 101, LED pin is a 1/2 Hz toggle pulse with 50 duty cycle. = 100, LED pin is a 1/4 Hz toggle pulse with 50 duty cycle. = 000, LED pin is drived low. Bit 3: GP port selection. 0, Select GP port 1 as LED function if bit 7 is set to 1. 1, Select GP port 2 as LED function if bit 7 is set to 1. As W83602R/G, setting this bit 1 is meaningless. Bit 2-0: GP pin selection. =110-000, GP16-GP10 can be selected as LED output when bit 3 is 0. =101-011, GP25-GP23 can be selected as LED output when bit 3 is 1. As W83602R/G, only GP16-GP10 can be selected as LED output. CR16-1F Reserved Register CR20 (Chip ID High Byte, Read Only) Bit 7-0: = 0x60. CR21 (Chip ID Low Byte, Read Only) Bit 7-0: = 0x13 (for W83601R/G). = 0x23 (for W83602R/G). NOTE: W83602R/G has no GP22-GP26. All the corresponding register has no effect on W83602R/G.
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Publication Release Date: May 26, 2005 Revision 1.0
W83601R/G/W83602R/G
8. FUNCTION DESCRIPTIONS
8.1 ACCESS INTERFACE
W83601R/G/W83602R/G provides a two-wired serial interface which is compliant with SMBusTM 1.0 Write Byte and Read Byte protocol.
8.1.1
Write a data into W83601R/G/W83602R/G register
0 SCL SDA
Start By Master
7
8
0
7
8
0
0
1
1
A2
A1
A0
R/W 0
Ack by 601R
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 601R
Frame 1 Serial Bus Address Byte
Frame 2 Internal Index Register Byte 7 8
SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0
Ack by 601R Stop by Master
Frame 3 Data Byte
8.1.2
Read a data from W83601R/G/W83602R/G register
0 SCL SDA
Start By Master
7
8
0
4
7
8 ...
0
0
1
1
A2
A1
A0
R/W 0
Ack by 601R
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 601R
...
Frame 1 Serial Bus Address Byte
Frame 2 Pointer Byte
0 SCL (Cont..) SDA (Cont..)
Repea Start By Master
7
8
0
7
8
0
0
1
1
A2
A1
A0
Frame 3 Serial Bus Address Byte
R/W 1
D7
Ack by 601R
D6
D5
D4
D3
D2
D1
D0
No Ack by Master Stop by Master
Frame 4 MSB Data Byte
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W83601R/G/W83602R/G
8.2 CTLSTRV Timing Waveforms (Only for W83602R/G)
SUSPEND FIRST AC ON POWER ON ~ S5 STATE ~ ~ S0 STATE ~ to RAM ~ S3 STATE ~ RESUME from S3 SOFT OFF ~ S5 STATE ~ ~ S0 STATE ~
5VSB S5IN# PWRCTL# PS_ON#
T2=500+125MS POWER *NOTE1 STR *NOTE2 T1= 5+1MS
T1=5+1MS
CTLSTRV DRAM_VOLTAG
3VCC 3VSB 3VCC
*NOTE 1: IT CAN WAKE UP POWER FROM POWER BUTTON, KEYBOARD/MOUSE, *NOTE 2: IT CAN SUSPEND TO RAM BY OS OR SPECIAL DEFINED
8.3
CTL3VSB Timing Waveforms (Only for W83602R/G)
Suspend to RAM Resume from S3 ~ S3 STATE ~ ~ S0 state ~
First AC On ~ S5 state ~
Power On ~ S0 state ~
Soft OFF ~ S5 state ~
5VSB PWRCTL#
t1= 5+1ms t1= 5+1ms
PS_ON#
T2=500+125MS T2=500+125MS
CTL3VSB 3VSB_Voltage
3VSB 3VCC 3VSB 3VCC 3VSB
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Publication Release Date: May 26, 2005 Revision 1.0
W83601R/G/W83602R/G
8.4
8.4.1
GPI/O Output Mode :
GPO output
GPO OUTPUT STYLE OUTPUT PORT REGISTER OUTPUT VALUE AT PIN
Tow output modes for GPO. One is LEVEL and the other is PULSE.
POLARITY WAVE
0 Level Pulse 1 0 1
0 1 0 1 write 1 write 1
0 1 1 0 Active Active
8.4.2
INT output
INT OUTPUT MODE POLARITY OUTPUT WAVE
Two output modes for INT pin. One is LEVEL mode and the other is PULSE.
Level Pulse
0(normal low) 1(normal high) 0(normal low) 1(normal high)
1 0 High Pulse Low Pulse
In Level mode, if INT is activated, it will be de-activated when interrupt status registers are read. In Pulse mode, interrupt will be activated again unless all enabled interrupt status registers are read.
8.4.3
GPI interrupt status
Once a transition occurs at GPI input pins, interrupt status registers (CR10, CR11) will be set. At the mean time, if interrupt function is enable, INT pin will generate an interrupt. Reading these interrupt registers will clear themselves and reset interrupt. If an interrupt occurs but no read to interrupt status registers, interrupt will not be generated again.
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W83601R/G/W83602R/G
9. DC AND AC SPECIFICATION
9.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage Input Voltage Operating Temperature Storage Temperature
-0.5 to 7.0 -0.5 to VDD+0.5 0 to +70 -55 to +150
V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
9.2
DC Characteristics
PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
(Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V)
I/OD12ts - TTL level bi-directional pin open drain with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Output Low Voltage Input High Leakage Input Low Leakage INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INts VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A V V V +10 -10 A A VIN = VDD VIN = 0 V VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V A A VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA VIN = VDD VIN = 0V
- TTL level Schmitt-triggered input pin VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 1.1 2.4 VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage
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Publication Release Date: May 26, 2005 Revision 1.0
W83601R/G/W83602R/G
DC Characteristics, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
INcd - CMOS level input pin with internal pull down Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 0.7VDD +10 -10 0.3 VDD V V A A V V 0.4 3.5 +10 -10 V V A A V V 0.4 +10 -10 V A A V IOL = 24 mA VIN = 5 V VIN = 0 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
I/O21 - CMOS level bi-direction pin with 21mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 0.7VDD 0.3 VDD VDD = 5 V VDD = 5 V IOL = 21 mA IOH = 21 mA VIN = VDD VIN = 0 V
I/OD24t - TTL level bi-direction pin open-drain output with 24mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.8
OD24 - open-drain output pin with 24mA sink capability Input Low Voltage VIL 0.4 IOL = 24 mA
9.3
9.3.1
AC Characteristics
Serial Bus Timing Diagram
t SCL t F tR
SCL
t HD;STA
t SU;DAT t SU;STO
SDA IN
VALID DATA
t HD;DAT
SDA OUT Serial Bus Timing Diagram
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W83601R/G/W83602R/G
Serial Bus Timing
PARAMETER SYMBOL MIN. MAX. UNIT
-
SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time SCL and SDA rise time SCL and SDA fall time
t SCL tHD;STA tSU;STO tSU;DAT tHD;DAT tR tF
10 4.7 4.7 120 5 1.0 300
uS uS uS nS nS uS nS
10. PACKAGE DRAWING AND DIMENSIONS
20 SSOP-209 mil
D
2
11
DIMENSION IN MM SYMBOL MIN. NOM MAX.
DIMENSION IN INCH MIN. NOM MAX.
DTEAIL A
HE E
A A1 A2 b c D E HE
2.00 0.05 1.65 0.22 0.09 6.90 5.00 7.40 0.55 1.75 1.85 0.38 0.25 7.50 5.60 8.20 0.95 0.10 8 0.002 0.065 0.009 0.004 0.272 0.197 0.291 0.021 0.283 0.209 0.307 0.0256 0.030 0.050 0.069
0.079 0.073 0.015 0.010 0.295 0.220 0.323 0.037 0.004 0 8
7.20 5.30 7.80 0.65 0.75 1.25
1
10
e L L1 Y
A2 A
SEATING PLANE
Y
SEATING PLANE
0
e
b
DETAIL A A1
L L1
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Publication Release Date: May 26, 2005 Revision 1.0
W83601R/G/W83602R/G
W83602R/G Example Application Circuit
R10 SCL SDA R9 C1 C2
Diagnostic LEDs
VCC R12 5VSB 1 2 3 4 5 This reset signal can be from system reset or GPO signal VCC 5 4 3 2 1 Q9 R11 4.7K 10 6 7 8 9 2N3904 10 9 8 7 6 D1 D2 D3 D4 D5 PCIRST# GP17 GP16 GP15 GP14 GP13 GP12 PWRCTL# PS_ON# To Power Supply PS_ON# signal W83601R/602R Q10 2N3904 12VCC 5VSB 5VSB 5VCC R8 4.7K 5VSB 5VCC GP10 GP11 GP12 GP13 GP14 R9 1K Q11 2N3904 SMBus Address 30 100
Reserved for needed U2
Note 1.
GP20 GP21 R1 10K R2 10K CTL3VSB GP10 GP11 CTLSTRV SLP_S5#
1 2 3 4 5 6 7 8 9 10
SCLK SDAT GP20/A0 GP21/A1 GP22/A2/CTL3VSB GP10 GP11 GP23/CTLSTRV GP24/S5IN# VSS
VCC RST# GP17/INT GP16 GP15 GP14 GP13 GP12 GP26/INT/PWCTLIN# GP25/PS_ON#
20 19 18 17 16 15 14 13 12 11
From W83627F/HF power control
Pull-up resistors
R10 1K
R11 4.7K S G R13 s Q1 Q4 NPN 3904 330 U1 VIN VOUT ADJ LT1084_M 3 2 1 R14 R VCC3_3VSB D PMOS IRF9531 Q2 D NMOS H603AL NPN 3904 G Q5 Q3
R12 4.7K
GP22 CTL3VSB
PWRGOOD NPN 3904 From system power good signal. This signal should be +5V high level.
Q12 2N3904
Q13 2N3904
C6 CAP
R15 R
JP10 1 2 HEADER2
5VSB 5VSB 5VCC
R16 1K
R17 4.7K S G R18 Q6 Q7 NPN 3904 330 PMOS IRF9531 D D17 1N5817
GP23 CTLSTRV
U3 VIN VOUT ADJ LT1084_M 3 2 VRAM 1 R20 R JP13 1 2 C7 CAP R21 R HEADER2 VRAM voltage is for RAM module VCC.
Note 1. : Be sure that during Power-On reset or RST# reset, GP20 and GP21 will not receive signal which will affect the SMBus address setting.
Winbond Electronic Corp. Title W83601R/602R Example Application Circuit Size Document Number Custom 602ap.sch Date: Friday, December 24, 1999 Sheet 1 of 1 Rev 0.3
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W83601R/G/W83602R/G
REV 0.1
Decription First Publication
0.2 0.3
Change CTL3VSB, CTLSTRV Schematic Change PMOS source,drain direction
Winbond Electronic Corp. Title W83601R/602R Example Application Circuit Size Document Number Custom 602ap.sch Date: Friday, December 24, 1999 Sheet 2 of 1 Rev 0.3
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Publication Release Date: May 26, 2005 Revision 1.0
W83601R/G/W83602R/G
11. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
n.a. 0.3 0.31 99/08 99/08 n.a. P.4,5 P.6 P.10 P.13 0.32 0.33 0.34 0.35 0.4 0.5 0.6 1.0 99/09 01/02 01/02 01/03 01/06 01/08 05/04 May 26, 2005 P.10 P.11 P.10 P.4 P.15 P.15 n.a. 20
All the version before 0.30 are for internal use. First publication. Change Pin Description of W83601R pin 3,4,5. Change Pin Description of W83602R pin 3,4. Update Register Table. CR16 is a reserved register. Please ignore it. Change INT output description. CR15 bit 3 description. Insert 8.1 section - Access interface Update CR21 Chip ID. Update pin characteristic. Update application schematic to version 0.3. Add chapter 9 DC and AC specification. Update chapter 9.2 DC specification Add Pb-free package ADD Important Notice
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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W83601R/G/W83602R/G
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Publication Release Date: May 26, 2005 Revision 1.0

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